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? semiconductor components industries, llc, 2015 october, 2015 ? rev. 7 1 publication order number: esd8104/d esd8104 esd protection diode low capacitance array for high speed data lines the esd8104 is designed to protect high speed data lines from esd. ultra?low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. the flow?through style package allows for easy pcb layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as usb 3.0/3.1 and hdmi 2.0. features ? low capacitance (0.37 pf max, i/o to gnd) ? protection for the following iec standards: iec 61000?4?2 (level 4) ? low esd clamping voltage ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? usb 3.0/3.1 ? esata ? hdmi 1.3/1.4/2.0 ? displayport maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ?55 to +125 c storage temperature range t stg ?55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000?4?2 contact (esd) iec 61000?4?2 air (esd) esd esd 15 15 kv kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. see application note and8308/d for further description of survivability specs. marking diagram device package shipping ordering information udfn10 case 517bb pin configuration and schematic www. onsemi.com esd8104mutag udfn10 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 4c m 4c = specific device code (tbd) m = date code = pb?free package i/o i/o i/o i/o gnd n/c n/c n/c n/c gnd 145 23 10 7 6 98 (note: microdot may be in either location) i/o pin 1 i/o pin 2 i/o pin 4 i/o pin 5 pins 3, 8 note: common gnd ? only minimum of 1 gnd connection required = SZESD8104MUTAG udfn10 (pb?free) 3000 / tape & reel
esd8104 www. onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current r dyn dynamic resistance *see application note and8308/d for detailed explanations of datasheet parameters. uni?directional tvs i pp i pp v i i r i t v rwm v cl v br v cl r dyn r dyn electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 3.3 v breakdown voltage v br i t = 1 ma, i/o pin to gnd 4.0 5.0 v reverse leakage current i r v rwm = 3.3 v, i/o pin to gnd 1.0 a clamping voltage (note 1) v c iec61000?4?2, 8 kv contact see figures 1 and 2 v clamping voltage tlp (note 2) see figures 5 through 8 v c i pp = 8 a i pp = ?8 a iec 61000?4?2 level 2 equivalent ( 4 kv contact, 4 kv air) 8.5 ?4.5 v i pp = 16 a i pp = ?16 a iec 61000?4?2 level 4 equivalent ( 8 kv contact, 15 kv air) 11.4 ?8.0 dynamic resistance r dyn i/o pin to gnd gnd to i/o pin 0.36 0.44 junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd v r = 0 v, f = 1 mhz between i/o pins v r = 0 v, f = 1 mhz, t a = 65 c between i/o pins and gnd 0.30 0.15 0.37 0.37 0.20 0.47 pf 1. for test procedure see figures 3 and 4 and application note and8307/d. 2. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. figure 1. iec61000?4?2 +8 kv contact clamping voltage figure 2. iec61000?4?2 ?8 kv contact clamping voltage time (ns) time (ns) voltage (v) voltage (v) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?20 0 20 40 60 80 100 140 120 90 80 70 60 50 40 30 20 10 0 ?10 ?20 0 20 40 60 80 100 140 120 10
esd8104 www. onsemi.com 3 iec 61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000?4?2 spec figure 4. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8307/d ? characterization of esd clamping performance. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd8104 www. onsemi.com 4 figure 5. positive tlp i?v curve figure 6. negative tlp i?v curve tlp current (a) v c , voltage (v) equivalent v iec (kv) 20 18 16 14 12 10 8 6 4 2 00 8 6 4 2 020 18 16 14 2468 12 10 tlp current (a) equivalent v iec (kv) ?20 0 8 6 4 2 020 18 16 14 2468 12 10 v c , voltage (v) ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. v iec is the equivalent voltage stress level calculated at the secondary peak of the iec 61000?4?2 waveform at t = 30 ns with 2 a/kv. see tlp description below for more information. 10 10 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 7. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 8 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. for more information on tlp measurements and how to interpret them please refer to and9007/d. figure 7. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 8. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms
esd8104 www. onsemi.com 5 with esd8104 without esd8104 figure 9. usb 3.0 eye diagram with and without esd8104. 5 gb/s with esd8104 without esd8104 figure 10. hdmi 2.0 eye diagram with and without esd8104. 6 gb/s with esd8104 without esd8104 figure 11. usb 3.1 eye diagram with and without esd8104. 10 gb/s see application note and9075/d for further description of eye diagram testing methodology.
esd8104 www. onsemi.com 6 figure 12. rf insertion loss table 1. rf insertion loss: application description interface data rate (gb/s) fundamental frequency (ghz) 3 rd harmonic frequency (ghz) esd8104 insertion loss (db) usb 3.0 5.0 2.5 (m1) 7.5 (m4) m1 = 0.128 m2 = 0.155 m3 = 0.352 m4 = 0.659 m5 = 0.958 m6 = 4.194 hdmi 2.0 6.0 3.0 (m2) 9.0 (m5) usb 3.1 10 5.0 (m3) 15 (m6)
esd8104 www. onsemi.com 7 figure 13. usb 3.0/3.1 type?a layout diagram vbus stda_sstx+ d? stda_sstx? d+ gnd_drain gnd stda_ssrx+ stda_ssrx? usb 3.0/3.1 type a connector esd8104 esd7l5.0 black = top layer red = other layer
esd8104 www. onsemi.com 8 figure 14. usb 3.1 type?c layout diagram tx1? vbus cc1 (config. detect: vconn or pd comm.) d+ d? sbu1 sideband use: aux signal vbus rx2? gnd tx1+ gnd rx1+ rx2+ vbus d? cc2 tx2+ tx2? vbus esd9x black = top layer red = bottom layer type?c hybrid top mount connector top layer type?c hybrid top mount connector bottom layer rx2+ gnd sbu2 d+ gnd esd9x
esd8104 www. onsemi.com 9 figure 15. hdmi layout diagram hdmi type a connector scl 5v cec gnd d0? gnd d0+ d2? d2+ hpd (and hec_dat) gnd sda clk? clk+ gnd d1+ d1? gnd n/c (or hec_dat) esd8104 esd8104 nup4114
esd8104 www. onsemi.com 10 pcb layout guidelines steps must be taken for proper placement and signal trace routing of the esd protection device in order to ensure the maximum esd survivability and signal integrity for the application. such steps are listed below. ? place the esd protection device as close as possible to the i/o connector to reduce the esd path to ground and improve the protection performance. ? in usb 3.0/3.1 applications, the esd protection device should be placed between the ac coupling capacitors and the i/o connector on the tx differential lanes as shown in figure 16. ? make sure to use differential design methodology and impedance matching of all high speed signal traces. ? use curved traces when possible to avoid unwanted reflections. ? keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ? place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk. figure 16. usb 3.0/3.1 connection diagram
esd8104 www. onsemi.com 11 esd protection device technology on semiconductor?s portfolio contains three main technologies for low capacitance esd protection device which are highlighted below and in figure 17. ? esd7000 series: zener diode based technology. this technology has a higher breakdown voltage (vbr) limiting it to protecting chipsets with larger geometries. ? esd8000 series: silicon controlled rectifier (scr) type technology. the key advatange for this technology is a low holding voltage (vh) which produces a deeper snapback that results in lower voltage over high currents as shown in the tlp results in figure 18. this technology provides optimized protection for chipsets with small geometries against thermal failures resulting in chipset damage (also known as ?hard failures?). ? esd8100 series: low voltage punch through (lvpt) type technology. the key advatange for this technology is a very low turn-on voltage as shown in figure 19. this technology provides optimized protection for chipsets with small geometries against recoverable failures due to voltage peaks (also known as ?soft failures?). figure 17. on semiconductor?s low-cap esd technology portfolio figure 18. high current, tlp, iv characteristic of each technology tlp current (a) esd8004 esd8104 esd7004 0 2 4 6 8 10 12 14 16 18 20 0246810121416 v c (v) equivalent v iec (kv) 18 20 0 2 4 6 8 10
esd8104 www. onsemi.com 12 figure 19. low current, dc, iv characteristic of each technology 1.00e?11 1.00e?10 1.00e?09 1.00e?08 1.00e?07 1.00e?06 1.00e?05 1.00e?04 1.00e?03 1.00e?02 1.00e?01 012345678 i (a) v (v) esd8104 esd8004 esd7004
esd8104 www. onsemi.com 13 package dimensions udfn10 2.5x1, 0.5p case 517bb issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal. c seating plane d b e 0.10 c a3 a a1 2x 2x 0.10 c dim a min millimeters 0.45 a1 0.00 a3 0.13 ref b 0.15 d 2.50 bsc b2 0.35 e 1.00 bsc e 0.50 bsc pin one reference 0.08 c 0.10 c 10x a 0.10 c note 3 l e b2 b b 5 6 8x 1 10 10x 0.05 c 0.30 l *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 0.45 0.50 dimensions: millimeters 1.30 pitch 0.25 10x 0.55 0.05 0.25 0.45 0.40 max ??? ??? a1 a3 detail b mold cmpd exposed cu optional construction l1 detail a l optional constructions l --- l1 0.05 top view side view bottom view detail b detail a outline package a 2x recommended 2x 8x on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 esd8104/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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